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IS41C16256-50TI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS41C16256-50TI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 19 page Integrated Silicon Solution, Inc. — 1-800-379-4774 1 Rev. J 06/29/00 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. IS41C16256 IS41LV16256 ISSI® FEATURES • TTL compatible inputs and outputs • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply 5V ± 10% (IS41C16256) 3.3V ± 10% (IS41LV16256) • Byte Write and Byte Read operation via two CAS • Extended Temperature Range -30 oC to 85oC • Industrail Temperature Range -40 oC to 85oC DESCRIPTION The ISSI IS41C16256 and IS41LV16256 are 262,144 x 16-bit high-performanceCMOSDynamicRandomAccessMemory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16256 and IS41LV16256idealforusein16and32-bitwidedatabussystems. These features make the IS41C16256 and IS41LV1626 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C16256 and IS41LV16256 are packaged in 40-pin 400-mil SOJ and TSOP (Type II). 256K x 16 (4-MBIT) DYNAMIC RAM JUNE 2000 WITH EDO PAGE MODE KEY TIMING PARAMETERS Parameter -35 -50 -60 Unit Max. RAS Access Time (tRAC) 3550 60ns Max. CAS Access Time (tCAC) 1014 15ns Max. Column Address Access Time (tAA) 1825 30ns Min. EDO Page Mode Cycle Time (tPC) 1220 25ns Min. Read/Write Cycle Time (tRC) 60 90 110 ns PIN CONFIGURATIONS 40-Pin TSOP (Type II) 40-Pin SOJ PIN DESCRIPTIONS A0-A8 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vcc Power GND Ground NC No Connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND |
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