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AR0134CSSM25SUEAD-GEVK Datasheet(PDF) 11 Page - ON Semiconductor |
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AR0134CSSM25SUEAD-GEVK Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 38 page AR0134CS/D Rev. 8, Pub. 1/16 EN 11 ©Semiconductor Components Industries, LLC,2016. AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor Configuration and Pinout Table 3: Pin Descriptions - 63-Ball iBGA Package Name iBGA Pin Type Description SLVS0_N A2 Output HiSPi serial data, lane 0, differential N. SLVS0_P A3 Output HiSPi serial data, lane 0, differential P. SLVS1_N A4 Output HiSPi serial data, lane 1, differential N. SLVS1_P A5 Output HiSPi serial data, lane 1, differential P. STANDBY A8 Input Standby-mode enable pin (active HIGH). VDD_PLL B1 Power PLL power. SLVSC_N B2 Output HiSPi serial DDR clock differential N. SLVSC_P B3 Output HiSPi serial DDR clock differential P. SLVS2_N B4 Output HiSPi serial data, lane 2, differential N. SLVS2_P B5 Output HiSPi serial data, lane 2, differential P. VAA B7, B8 Power Analog power. EXTCLK C1 Input External input clock. VDD_SLVS C2 Power HiSPi power. (May leave unconnected if parallel interface is used) SLVS3_N C3 Output (Unsupported) HiSPi serial data, lane 3, differential N. SLVS3_P C4 Output (Unsupported) HiSPi serial data, lane 3, differential P. DGND C5, D4, D5, E5, F5, G5, H5 Power Digital GND. VDD A6, A7, B6, C6, D6 Power Digital power. AGND C7, C8 Power Analog GND. SADDR D1 Input Two-Wire Serial address select. SCLK D2 Input Two-Wire Serial clock input. SDATA D3 I/O Two-Wire Serial data I/O. VAA_PIX D7, D8 Power Pixel power. LINE_VALID E1 Output Asserted when DOUT line data is valid. FRAME_VALID E2 Output Asserted when DOUT frame data is valid. PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock. FLASH E4 Output Control signal to drive external light sources. VDD_IO E6, F6, G6, H6, H7 Power I/O supply power. DOUT8 F1 Output Parallel pixel data output. DOUT9 F2 Output Parallel pixel data output. DOUT10 F3 Output Parallel pixel data output. DOUT11 F4 Output Parallel pixel data output (MSB) TEST F7 Input Manufacturing test enable pin (connect to DGND). DOUT4 G1 Output Parallel pixel data output. DOUT5 G2 Output Parallel pixel data output. DOUT6 G3 Output Parallel pixel data output. DOUT7 G4 Output Parallel pixel data output. TRIGGER G7 Input Exposure synchronization input. (Connect to DGND if HiSPi interface is used) OE_BAR G8 Input Output enable (active LOW). DOUT0 H1 Output Parallel pixel data output (LSB) DOUT1 H2 Output Parallel pixel data output. DOUT2 H3 Output Parallel pixel data output. DOUT3 H4 Output Parallel pixel data output. |
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