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AR0134CSSM00SPCA0-DRBR Datasheet(PDF) 9 Page - ON Semiconductor |
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AR0134CSSM00SPCA0-DRBR Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 38 page AR0134CS/D Rev. 8, Pub. 1/16 EN 9 ©Semiconductor Components Industries, LLC,2016. AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor Configuration and Pinout Figure 5: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The serial interface output pads can be left unconnected if the parallel output interface is used. 5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Refer to the AR0134 demo headboard schematics for circuit recom- mendations. 6. ON Semiconductor recommends that analog power planes be placed in a manner such that cou- pling with the digital power planes is minimized. VDD Master clock (6–50 MHz) SDATA SCLK TEST FLASH FRAME_VALID DOUT [11:0] EXTCLK DGND Digital ground Analog ground Digital core power1 To controller From Controller LINE_VALID PIXCLK RESET_BAR VDD_IO Digital I/O power1 VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1 VAA_PIX VDD_IO VDD_PLL VDD VAA TRIGGER OE_BAR STANDBY AGND |
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