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AR0237CSSC12SPRAH3-GEVB Datasheet(PDF) 6 Page - ON Semiconductor

Part # AR0237CSSC12SPRAH3-GEVB
Description  1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AR0237CSSC12SPRAH3-GEVB Datasheet(HTML) 6 Page - ON Semiconductor

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AR0237CS/D Rev. 4, 6/16 EN
6
©Semiconductor Components Industries, LLC, 2016.
AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Functional Overview
Functional Overview
The AR0237 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master input clock running between
6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock
rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor configured in linear
mode, and in HDR mode.
Figure 1:
Block Diagram of AR0237
User interaction with the sensor is through the two-wire serial bus, which communi-
cates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 2.1 Mp Active- Pixel Sensor array. The timing and control circuitry sequences
through the rows of the array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the pixels in the row integrate
incident light. The exposure is controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the columns is sequenced through an
analog signal chain (providing offset correction and gain), and then through an analog-
to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in
the array. The ADC output passes through a digital processing signal chain (which
provides further data path corrections and applies digital gain). The sensor also offers a
Row Noise Correction
Black Level Correction
Test Pattern Generator
Pixel Defect Correction
Digital Gain and Pedestal
A-Law Compression
Parallel
HiSPi
12 bits
10 bits
12
12
ADC Data


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