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TPS80032A2ABYFFR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS80032A2ABYFFR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 127 page  TPS80032 www.ti.com SWCS059I – MARCH 2011 – REVISED NOVEMBER 2014 3.2 Pin Attributes Pin Attributes PULLUP / CONNECTION IF NAME BALL TYPE I/O DESCRIPTION PULLDOW NOT USED N System Supply Regulator/Battery Charger Switched-mode regulator boot-strapped CHRG_BOOT E2 Analog O Floating – capacitor for the high-side MOSFET gate driver Switched-mode regulator current-sense input CHRG_CSIN D4 Analog I Ground – (without power path) Switched regulator auxiliary power supply, connected to the system supply/battery to CHRG_CSOUT D5 Analog I provide power in high-impedance mode, System supply – switched regulator system/battery voltage/current sense input USB charging port detection signal from USB CHRG_DET_N A4 Analog I Ground – PHY CHRG_EXTCHRG_EN Output control signal to an external VAC charger F4 Digital O Floating – Z (default high) PU CHRG_EXTCHRG_ST F3 Digital I External VAC charger status input pin Floating 70 to 190 ATZ k Ω CHRG_LED_IN A6 Power I Input supply for LED indicator Ground – CHRG_LED_TEST B6 Analog I/O External LED driver output Ground – A5, CHRG_PGND B5, Ground I Switched regulator power ground Ground – C5 A2, Switched regulator connection point between CHRG_PMID B2, Analog O reverse blocking MOSFET and high-side Floating – C2 switching MOSFET A3, B3, CHRG_SW C3, Power O Switched regulator output for inductor connection Floating – B4, C4 CHRG_VREF D2 Analog O Switched regulator internal bias regulator voltage Floating – VAC C6 Power I VAC charger input sense line Ground – Ground (must be connected to B1, VBUS if VBUS VBUS input, USB system supply/battery charger VBUS C1, Power I/O detection from – power supply D1 PMIC is needed; for example, USB boot up) CHRG_VSYS C12 Power I System supply System supply – CHRG_VBAT B13 Power I/O Battery voltage for battery charging System supply – VBUS_DET F7 Digital O VBUS detection signal (VSYS level) Floating – Control signal for gate of external PMOS (battery CHRG_GATE_CTRL C13 Analog O Floating – switch) Control signal for gate of external PMOS to CHRG_PROT_GATE G1 Analog O Floating – protect against negative input voltage (optional) Power Supplies C7, GND_ANA E1, Ground I Analog power ground Ground – H8, L9 GND_DIG_VIO L7 Ground I VIO digital ground Ground – GND_DIG_VRTC G3 Ground I VRTC digital ground Ground – Copyright © 2011–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: TPS80032 |
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