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| IRU3013 |
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IRF |
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5 page
IRU3013 5 Rev. 1.2 09/06/01 BLOCK DIAGRAM Figure 2 - Simplified block diagram of the IRU3013. PWM Control V12 V12 Osc Slope Comp + 0.8V 5Bit DAC, Ctrl Logic Enable Soft Start & Fault Logic 200uA 0.9Vset 1.1Vset Vset Enable UVLO Vset Enable VFB4 Lin4 Lin1 VFB1 D25 V5 V12 SS Gnd PGd CS- Ct CS+ LDrv HDrv VFB3 D3 D2 D1 D0 Over Current Enable PGnd 1.17Vset OVP 1.2V VFB2 Lin2 18 10 11 13 8 9 1 17 6 7 12 14 5 23 22 21 20 19 3 2 24 4 16 15 |