TPS795

SLVS350I – OCTOBER 2002 – REVISED MAY 2015

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6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

IN

–0.3

6

Voltage

EN

–0.3

V

OUT

6

Current

Peak output

Internally limited

Power dissipation

Continuous total

See Thermal Information

–40

150

°C

Temperature

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

±2000

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage

2.7

5.5

V

Output current

0

0.5

A

Operating junction temperature

–40

125

°C

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

DRB (SOT-223)

DCQ (WSON)

UNIT

6 PINS

8 PINS

Junction-to-ambient thermal resistance

47.8

70.4

Junction-to-case (top) thermal resistance

83

70

Junction-to-top characterization parameter

2.1

6.8

°C/W

Junction-to-board characterization parameter

17.8

30.1

Junction-to-case (bottom) thermal resistance

12.1

6.3

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the DRB and DCQ packages are derived by thermal simulations based on JEDEC-standard methodology as specified

in the JESD51 series. The following assumptions are used in the simulations:

(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2-mm x 2-mm thermal via array.

(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper

coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, see Thermal Considerations and Estimating Junction Temperature

of this data sheet.

4

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