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MAX11905ETP Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX11905ETP Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 29 page (fSAMPLE = 1.6Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and device characterization. Note 3: See the Analog Inputs section. Note 4: See the Definitions section at the end of the data sheet. Note 5: See the Definitions section at the end of the data sheet. Error contribution from the external reference not included. Note 6: Parameter is guaranteed by design. Note 7: Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage. Note 8: Sine wave input, fIN = 10kHz, AIN = -0.5dB below full scale. Note 9: CLOAD = 10pF on DOUT. fCONV = 1.6Msps. All data is read out. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING DIN to SCLK Rising Edge Setup t1 4 ns DIN to SCLK Rising Edge Hold t2 1 ns DOUT End-Of-Conversion Low Time t3 10 ns DOUT to SCLK Rising Edge Hold t4 2.5 ns DOUT to SCLK Rising Edge Setup t5 100MHz SCLK 1.5 ns SCLK High t6 4.5 ns SCLK Period t7 10 ns SCLK Low t8 4.5 ns CNVST Rising Edge To SCLK Rising Edge t9 0 ns SCLK Rising Edge to CNVST Rising Edge t10 25 ns CNVST High t11 20 ns CNVST High to EOC t12 525 ns Conversion Period t13 625 ns MAX11905 20-Bit, 1.6Msps, Low-Power, Fully Differential SAR ADC www.maximintegrated.com Maxim Integrated │ 7 Electrical Characteristics (continued) |
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