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IDT70V26L55J Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT70V26L55J Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 17 page  6.42 IDT70V26S/L High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 2945 drw 12 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD tBAA AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (S or L). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office. Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/ S = VIL (SLAVE). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. If M/ S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example). 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 70V26X25 Com'l Only 70V26X35 Com'l Only 70V26X55 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S = VIH) tBAA BUSY Access Time from Address Match ____ 25 ____ 35 ____ 45 ns tBDA BUSY Disable Time from Address Not Match ____ 25 ____ 35 ____ 45 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 25 ____ 35 ____ 45 ns tBDC BUSY Disab le Time from Chip Enable High ____ 25 ____ 35 ____ 45 ns tAPS Arbitration Priority Set-up Time(2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 35 ____ 40 ____ 50 ns tWH Write Hold After BUSY(5) 20 ____ 25 ____ 25 ____ ns BUSY INPUT TIMING (M/S = VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 20 ____ 25 ____ 25 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 55 ____ 65 ____ 85 ns tDDD Write Data Valid to Read Data Delay (1) ____ 50 ____ 60 ____ 80 ns 2945 tbl 13 |
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