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TPS65980RHFR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS65980RHFR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 28 page  TPS65980 www.ti.com SLVSCK1A – APRIL 2014 – REVISED APRIL 2014 Electrical Characteristics (continued) Unless otherwise noted all specifications applies over the VTBT_IN range and operating ambient temperature of –40°C ≤ TA ≤ 85°C, CTBT_IN = 22 µF, CTBT_OUT = 10 µF, CCBL_OUT = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions. Typical values are for VTBT_IN = 12 V and TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEV_EN AND ILIMIT INPUT LOGIC VIH High-level input voltage 2.6 V VIL Low-level input voltage 0.6 V IIN Input leakage to GND VDEV_EN = 3.3V 1 mA RESET AND HV_OK OUTPUT LOGIC VOH High-level output voltage IL = –1.5 mA, Referenced to VTBT_OUT –250 0 mV VOL Low-level output voltage IL = 1.5 mA 0 250 mV SOFT START(8) IINRUSH Inrush current di/dt 250 kA/s THERMAL SHUTDOWN TSD Shutdown temperature 120 135 150 °C TSDHYST Shutdown hysteresis 10 °C (8) The charge pump will limit the normal ramp of current. Soft start will control the inrush current when the input ramps from 0 V to high voltage (not a normal operating condition). See recommended components section for required soft-start cap. 7.6 Timing Requirements MIN TYP MAX UNIT VTBT_IN ≥ 0.9 × VTBT_IN(min) to tIN2OR TBT_IN to TBT_OUT On Time VTBT_OUT ≥ 0.99 × VTBT_OUT(min) 20 ms RTBT_OUT = 100 Ω VTBT_IN ≤ 0.9 × VTBT_IN(min) to tIN2OF TBT_IN to TBT_OUT Off Time VTBT_OUT ≤ 0.1 × VTBT_OUT(min) 2.4 4 ms RTBT_OUT = 100 Ω VTBT_OUT ≥ VREF_RSTN(max) rising to tOUT2RR TBT_OUT to RESETZ High time 20 µs VRESET = 0.9 × VOH, CRESETN = 100 pF VTBT_IN ≤ 0.9 × VTBT_IN(min) to tIN2RF TBT_IN to RESETZ Low time 20 ms VRESET = 0.1 × VOH, CRESETN = 100 pF VTBT_IN ≥ VHVTR to VHV_OK = 0.9 × VOH tHV2OKR TBT_IN Rise to HV_OK 10 µs CHV_OK = 100 pF VTBT_IN ≤ VHVTR-VHVTHYST to tHV2OKF TBT_IN Fall to HV_OK 10 µs VHV_OK = 0.1 × VOH, CHV_OK = 100 pF VHV_OK ≥ 1.65 V to VCBL_OUT = 2.95 V tHV2CR (1) (2) HV_OK to CBL_OUT On time 0.1 10 ms RCB_OUT = 100 Ω, CHV_OK = 100 pF VHV_OK ≤ 1.65 V to VCBL_OUT = 2.95 V tHV2CF HV_OK to CBL_OUT Off time 40 µs RCB_OUT = 100 Ω, CHV_OK = 100 pF VCBL_OUT ramp 10% to 90% tRCBL CABLE_OUT Ramp time 0.1 10 ms CCBL_OUT = 0 to 52 µF VDEV_EN ≤ 1.65 V to VDEV_OUT = 2.7 V tDEVEN DEV_EN to DEV_OUT On time 0.1 10 ms RDEV_OUT = 100 Ω VDEV_EN ≥ 1.65V to VDEV_OUT = 2.7 V tDEVDIS DEV_EN to DEV_OUT Off time 50 ms RDEV_OUT = 100 Ω VHV_OK ≥ 1.65 V to VDEV_EN ≤ 1.65 V Wait time from HV_OK High before tHV2DEVEN 2 ms DEV_EN can be asserted low(2) CHV_OK = 100 pF (1) TBT_IN must transition from 3.3 V to high voltage, not from 0 V to high voltage (2) During the transition from low voltage input to high voltage input, the total load of all outputs combined can not exceed 85 mA until 2 ms after HV_OK asserts high. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS65980 |
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