Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

t

DSR1

Deserializer PLL

Lock Time from

PWRDWN (with

SYNCPAT)

(Note 7)

35MHz

3.7

10

µs

80 MHz

1.9

4

µs

t

DSR2

Deserializer PLL

Lock time from

SYNCPAT

35MHz

1.5

5

µs

80 MHz

0.9

2

µs

t

RNMI-R

Ideal Deserializer

Noise Margin Right

Figure 16

(Note 6)

35 MHz

+630

ps

80 MHz

+230

ps

t

RNMI-L

Ideal Deserializer

Noise Margin Left

Figure 16

(Note 6)

35 MHz

−630

ps

80 MHz

−230

ps

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,

∆VOD,

VTH and VTL which are differential voltages.

Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.

Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions

of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time

required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before

initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change

from not receiving data to receiving synchronization patterns (SYNCPATs).

Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement

in reference with the ideal bit position, please see National’s AN-1217 for detail.

Note 7: Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.

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