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CY7C43646AV-10AC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C43646AV-10AC
Description  3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C43646AV-10AC Datasheet(HTML) 6 Page - Cypress Semiconductor

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Document #: 38-06026 Rev. *C
Page 6 of 40
PRS2
FIFO2 Partial
Reset
I
A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RENB
Port B Read
Enable
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read data on
Port B.
RT1
FIFO1
Retransmit
I
A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing
the Read pointer back to location zero. The user will still need to perform Read opera-
tions to retransmit the data. Retransmit function applies to CY Standard mode only.
RT2
FIFO2
Retransmit
I
A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
the Read pointer back to location zero. The user will still need to perform Read opera-
tions to retransmit the data. Retransmit function applies to CY Standard mode only.
SIZEB
Bus Size Select
I
A HIGH on this pin selects byte bus (9-bit) size on Port B. A LOW on this pin selects
word (18-bit) bus size. SIZEB works with BE to select the bus size and endian
arrangement for Port B. The level of SIZEB must be static throughout device operation.
SIZEC
Bus Size Select
I
A HIGH on this pin selects byte bus (9-bit) size on Port C. A LOW on this pin selects
word (18-bit) bus size. SIZEC works with BE to select the bus size and endian
arrangement for Port C. The level of SIZEC must be static throughout device operation.
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I
A HIGH selects a Write operation and a LOW selects a Read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the HIGH impedance
state when W/RA is HIGH.
WENC
Port C Write
Enable
I
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on
Port C.
Pin Definitions (continued)
Signal Name
Description
I/O
Function


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