MPY634

7

SBFS017A

www.ti.com

normally referenced to output ground. Alternatively, as the

is made to a multiplying input, the effective gain of the

output op amp varies as a function of the denominator input

voltage. Therefore, the bandwidth of the divider function is

proportional to the denominator voltage (see Typical Perfor-

mance Curves).

FIGURE 5. Square-Rooter Connection.

APPLICATIONS

FIGURE 6. Phase Detector.

FIGURE 7. Voltage-Controlled Amplifier.

MPY634

X

1

+V

S

X

2

Out

SF

Z

1

Y

1

Z

2

Y

2

–V

S

–15V

+15V

V

0.1µF

R

X

A sin (2

π 10MHz t)

B sin (2

π 10MHz t + )

Multiplier connection followed by a low-pass filter forms phase

detector useful in phase-locked-loop circuitry. R

PLL circuitry to provide desired loop-damping characteristics.

1k

Ω

θ

θ

MPY634

X

1

+V

S

X

2

Out

SF

Z

1

Y

1

Z

2

Y

2

–V

S

–15V

+15V

Z Input

10V FS

12V PK

V

10V(Z

Output,

±12V PK

R

L

(Must be

provided)

Reverse

this and

X inputs

for

Negative

Outputs

Optional

Summing

Input, X,

±10V PK

FIGURE 4. Basic Divider Connection.

Accuracy of the divider mode typically ranges from 1.0% to

2.5% for a 10 to 1 denominator range depending on device

grade. Accuracy is primarily limited by input offset voltages

and can be significantly improved by trimming the offset of

the X input. A trim voltage of

±3.5mV applied to the “low

produce similar accuracies over 100 to 1 denominator range.

To trim, apply a signal which varies from 100mV to 10V at

a low frequency (less than 500Hz). An offset sine wave or

ramp is suitable. Since the ratio of the quantities should be

constant, the ideal output would be a constant 10V. Using

AC coupling on an oscilloscope, adjust the offset control for

minimum output voltage variation.

SQUARE-ROOTER

A square-rooter connection is shown in Figure 5. Input

voltage is limited to one polarity (positive for the connection

shown). The diode prevents circuit latch-up should the input

go negative. The circuit can be configured for negative input

and positive output by reversing the polarity of both the X

and Y inputs. The output polarity can be reversed by revers-

ing the diode and X input polarity. A load resistance of

approximately 10k

Ω must be provided. Trimming for im-

proved accuracy would be accomplished at the Z input.

MPY634

X

1

+V

S

X

2

V

O

SF

Z

1

Y

1

Z

2

Y

2

–V

S

–15V

+15V

OPA606

1k

Ω

Minor gain adjustments are accomplished with the 1k

Ω variable resistor

connected to the scale factor adjustment pin, SF. Bandwidth of this circuit

is limited by A

A

1

39k

Ω

2k

Ω

2k

Ω

+

–

E

S

+

–

E

C

–15V

V

MPY634

X

1

+V

S

X

2

Out

SF

Z

1

Y

1

Z

2

Y

2

–V

S

–15V

+15V

Optional

Summing Input

±10V PK

X Input

(Denominator)

0.1V

≤ X ≤ 10V

Z Input

(Numerator)

±10V FS,

±12V PK

+

–

(X

V

+ Y

1

10V(Z

Output, ±12V PK