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TPS65320C-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS65320C-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 41 page  7 TPS65320C-Q1 www.ti.com SLVSD50B – MARCH 2016 – REVISED JUNE 2016 Product Folder Links: TPS65320C-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating junction temperature TJ = 150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR Power supply ripple rejection V(VIN_LDO)(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA, frequency (ƒ) = 100 Hz, V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V 60 dB V(VIN_LDO)(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA, ƒ = 150 kHz, V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V 30 dB C(LDO_OUT) Output capacitor ESR = 0.001 Ω to 100 mΩ, large output capacitance may be required for load transient; V(LDO_OUT) ≥ 3.3 V 1 40 μF C(LDO_OUT) Output capacitor ESR = 0.001 Ω to 100 mΩ, large output capacitance may be required for load transient; 1.2 V ≤ V(LDO_OUT) < 3.3 V 20 40 μF LDO REGULATOR: RESET (nRST PIN) RESET threshold V(LDO_OUT) decreasing 85 90 95 % VOH Output high Reset released due to rising LDO_OUT, V(LDO_OUT) ≥ 3.3 V, IOH= 100 μA –5% × V(LDO_OUT) V VOL Output low Reset asserted due to falling LDO_OUT, IOL = 1 mA 0.045 0.4 V OVER TEMPERATURE PROTECTION TSD Thermal-shutdown trip point 175 ºC Thys Hysteresis 10 ºC 6.6 Switching Characteristics VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating junction temperature TJ = 150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BUCK REGULATOR: HIGH-SIDE MOSFET tonmin Minimum on-time ƒS = 2.5 MHz 115 ns BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) ƒS Switching-frequency range using RT mode 100 2500 kHz Switching frequency 200-k Ω resistor connected between pin RT/CLK and GND 523 585 640 kHz Switching-frequency range using CLK mode 300 2200 kHz Minimum CLK input pulse width Measures at CLK input = 2.2 MHz 30 ns RT/CLK Falling edge to SW rising edge delay Measured at 500 kHz with 200-k Ω series resistor connected to RT/CLK pin 60 ns PLL Lock-in time Measured at 500 kHz 100 μs LDO REGULATOR: RESET (nRST PIN) Filter time Delay before asserting nRST low 7 14 21 μs |
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