NCP347

http://onsemi.com

10

Undervoltage Lockout (UVLO)

To ensure proper operation under any conditions, the

device has a built−in undervoltage lockout (UVLO) circuit.

plus hysteresis, nominal. The FLAG output is tied to low as

a 60 mV hysteresis to provide noise immunity to transient

condition. Additional UVLO thresholds ranging from

UVLO can be manufactured. (See Selection Guide on page

12) Contact your ON Semiconductor representative for

availability.

Overvoltage Lockout (OVLO)

overvoltage, the device has a built−in overvoltage lockout

(OVLO) circuit. During overvoltage condition, the output

remains disabled as long as the input voltage exceeds

5.675 V typical (NCP347MTAE). Additional OVLO

thresholds ranging from OVLO can be manufactured. (See

Selection Guide on page 12) Contact your ON

Semiconductor representative for availability.

This circuit has a 90 mV hysteresis to provide noise

FLAG Output

The NCP347 provides a FLAG output, which alerts

external systems that a fault has occurred.

This pin is tied to low as soon the OVLO threshold is

FLAG is held high, keeping in mind that an additional

50 ms delay has been added between available output and

FLAG = high. The pin is an open drain output, thus a pull

up resistor (typically 1 M

W, minimum 10 kW) must be

device is turned off (EN = 1).

EN Input

To enable normal operation, the EN pin shall be forced

to low or connected to ground. A high level on the pin,

disconnects OUT pin from IN pin. EN does not overdrive

an OVLO or UVLO fault.

Internal NMOS FET

FET to protect the systems, connected on OUT pin, from

positive overvoltage. Regarding electrical characteristics,

ESD Tests

The NCP347 input pin fully supports the IEC61000−4−2.

1.0

GND, close to the device.

ESD protected input.

Please refer to Figure 19 to see the IEC 61000−4−2

electrostatic discharge waveform.

Figure 19. Electrostatic Discharge Waveform

PCB Recommendations

The NCP347 integrates a 2 amperes rated NMOS FET,

and the PCB rules must be respected to properly evacuate

the heat out of the silicon. The PAD1 is internally isolated

from the active silicon and should preferably be connected

to ground. The PAD2 of the NCP347 package is connected

to the internal NMOS drain and can be used to increase the

heat transfer if necessary from an applications standpoint.

Depending upon the power dissipated in the application,

one can either use the PCB tracks connected to Pins 4 and

5 to evacuate heat, or make profit of the PAD2 area to add

extra copper surface to reduce the junction temperature

(See Figure 20). Of course, in any case, this pad shall be not

connected to any other potential. Figure 20 shows copper

transfer plane connected to PAD2.