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DA14583 Datasheet(PDF) 5 Page - Dialog Semiconductor |
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DA14583 Datasheet(HTML) 5 Page - Dialog Semiconductor |
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5 / 148 page  © 2014 Dialog Semiconductor 5 Target - March 06, 2015 v1.1 Table 3: Pin Description PIN NAME TYPE Drive (mA) Reset state (Note ) DESCRIPTION General Purpose I/Os P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. P1_0 P1_1 P1_2 P1_3 P1_4/SW_CLK P1_5/SWDIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PU INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. This signal is the JTAG clock by default This signal is the JTAG data I/O by default P2_0/SPI_CLK P2_1 P2_2 P2_3/SPI_EN P2_4/SPI_DO P2_5 P2_6 P2_7 P2_8 P2_9/SPI_DI DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. Note: The specified pin assignment of the SPI interface is man- datory for booting from internal Flash memory. P3_0 to P3_7 DIO 4.8 I-PD Not supported Debug interface SWDIO/P1_5 DIO 4.8 I-PU INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Can also be used as a GPIO SW_CLK/P1_4 DIO 4.8 I-PD INPUT JTAG clock signal. Can also be used as a GPIO Clocks XTAL16Mp AI INPUT. Crystal input for the 16 MHz XTAL XTAL16Mm AO OUTPUT. Crystal output for the 16 MHz XTAL XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL Quadrature decoder QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports SPI bus interface SPI_CLK/P2_0 DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports SPI_DI/P2_9 DI INPUT. SPI Data input. Mapped on Px ports SPI_DO/P2_4 DO OUTPUT. SPI Data output. Mapped on Px ports |
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