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NCL30185ADR2G Datasheet(PDF) 7 Page - ON Semiconductor |
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NCL30185ADR2G Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 28 page NCL30185 www.onsemi.com 7 Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V) Description Unit Max Typ Min Symbol Test Condition CONSTANT CURRENT AND POWER FACTOR CONTROL Error amplifier current capability VREFX=VREF (no dimming) VREFX=25%* VREF IEA ±60 ±240 mA COMP Pin Start−up Current Source No dimming, COMP pin grounded IEA_STUP 140 mA LINE FEED FORWARD VVS to ICS(offset) conversion ratio KLFF 18 20 22 mS Line feed−forward current on CS pin DRV high, VVS = 2 V IFF 35 40 45 mA Offset current maximum value VVS > 5 V Ioffset(MAX) 80 100 120 mA VALLEY LOCKOUT SECTION Threshold for high− line range (HL) detection VVS rising VHL 2.28 2.40 2.52 V Threshold for low−line range (LL) detection VVS falling VLL 2.18 2.30 2.42 V Blanking time for line range detection tHL(blank) 15 25 35 ms Valley Lockout First step valley in High−Line. Second step valley in High−Line. Third step valley in High−Line. First step valley in Low−Line. Second step valley in Low−Line. Third step valley in Low−Line. VHL100% VHL70% VHL25% VLL100% VLL70% VLL25% 2 3 6 1 2 5 FREQUENCY FOLDBACK Additional dead time VREFX = 25%*VREF tFF1LL 1.4 2.0 2.6 ms Additional dead time VREFX = 5%*VREF tFF2HL − 40 − ms FAULT PROTECTION Thermal Shutdown (Note 6) FSW = 65 kHz TSHDN 130 150 170 _C Thermal Shutdown Hysteresis TSHDN(HYS) − 50 – _C Threshold voltage for output short circuit or aux. winding short circuit detection VZCD(short) 0.8 1.0 1.2 V Short circuit detection Timer VZCD < VZCD(short) tOVLD 70 90 110 ms Auto−recovery timer duration trecovery 3 4 5 s SD pin Clamp series resistor RSD(clamp) 1.6 k W Clamped voltage SD pin open VSD(clamp) 1.13 1.35 1.57 V SD pin detection level for OVP VSD rising VOVP 2.35 2.50 2.65 V Delay before OVP or OTP confirmation (OVP and OTP) TSD(delay) 22.5 30.0 37.5 ms Reference current for direct connection of an NTC (Note 8) IOTP(REF) 80 85 90 mA Fault detection level for OTP (Note 7) VSD falling VOTP(off) 0.47 0.50 0.53 V SD pin level for operation recovery after an OTP detection VSD rising VOTP(on) 0.66 0.70 0.74 V 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. |
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