LC898124EP1XC

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9

2-wire serial Interface Timing

The communication protocol is compatible with I

This circuit has clock stretch function.

Item

Symbol

Pin

name

Min

Typ

Max

Units

SCL clock frequency

Fscl

SCL

1000

kHz

START condition hold time

tHD,STA

SCL

SDA

0.26

s

SCL clock Low period

tLOW

SCL

0.5

s

SCL clock High period

tHIGH

SCL

0.26

s

Setup time for repetition

START condition

tSU,STA

SCL

SDA

0.26

s

Data hold time

tHD,DAT

SCL

SDA

0 (*1)

0.9

s

Data setup time

tSU,DAT

SCL

SDA

50

ns

SDA, SCL rising time

tr

SCL

SDA

120

ns

SDA, SCL falling time

tf

SCL

SDA

120

ns

STOP condition setup time

tSU,STO

SCL

SDA

0.26

s

Bus free time between

STOP and START

tBUF

SCL

SDA

0.5

s

(*1) Although the I

This LSI is designed for a condition with typ. 40 ns of hold time. If SDA signal is unstable around

falling point of SCL signal, please implement an appropriate treatment on board, such as inserting

a resistor.

SDA

SCL