ADP3120A

http://onsemi.com

2

Figure 1. Block Diagram

8

1

4

7

5

6

2

3

DRVH

BST

SWN

DRVL

PGND

OD

IN

TSD

UVLO

MONITOR

FALLING

EDGE

DELAY

MONITOR

FALLING

EDGE

DELAY

NON−OVERLAP

TIMERS

MIN DRVL

OFF TIMER

START

STOP

PIN DESCRIPTION

SO−8

DFN8

Symbol

Description

1

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds

this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value

is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.

2

2

IN

Logic−Level Input. This pin has primary control of the drive outputs.

3

3

OD

Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.

4

4

Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.

5

5

DRVL

Output drive for the lower MOSFET.

6

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

7

SWN

Switch Node. Connect to the source of the upper MOSFET.

8

8

DRVH

Output drive for the upper MOSFET.