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AVAILABLE OPTIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

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TPS2375

TPS2376

TPS2377

SLVS525A – APRIL 2004 – REVISED SEPTEMBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

UVLO THRESHOLDS (NOMINAL)

MARKING

TYPE

LOW

HIGH

SO-8

TSSOP-8

802.3af

30.5 V

39.3 V

TPS2375D

TPS2375PW

2375

-40

°C to 85°C

Adjustable

1.93 V

2.49 V

TPS2376D

TPS2376PW

2376

Legacy

30.5 V

35.1 V

TPS2377D

TPS2377PW

2377

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Add an R suffix to thedevice type for tape and reel.

(VSS)

TPS237x

-0.3 V to 100 V

Voltage

ILIM, UVLO

-0.3 V to 10 V

CLASS

-0.3 V to 12 V

0 to 515 mA

Current, sinking

PG

0 to 5 mA

DET

0 to 1 mA

CLASS

0 to 50 mA

Current, sourcing

ILIM

0 to 1 mA

Human body model

2 kV

ESD

Charged device model

500 V

8/15 kV

Maximum junction temperature range

Internally limited

Storage temperature range

-65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Green Packages

260

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds - Nongreen Packages

235

°C

(1)

Stresses beyond those listedunder “absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings

only, and functional operation of the deviceat these or any other conditions beyond those indicated under“recommended operating

conditions” is not implied. Exposure toabsolute–maximum–rated conditions for extended periods may affectdevice reliability.

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Surges applied to RJ-45 ofFigure 1 between pins of RJ-45,and between pins and output voltage rails per EN61000-4-2,1999.

POWER RATING

θ

θ

(HIGH-K)

PACKAGE

°C/W

°C/W

mW

D (SO-8)

238

150

266

PW (TSSOP-8)

258.5

159

251

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Tested per JEDEC JESD51.High-K is a (2 signal – 2 plane) test board and low-K is a double

sidedboard with minimum pad area and natural convection.

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