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PCA9848PWJ Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCA9848PWJ Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 32 page  PCA9848 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 1 — 15 December 2014 11 of 32 NXP Semiconductors PCA9848 8-channel ultra-low voltage, Fm+ I2C-bus switch with reset 6.6 Power-on reset requirements In the event of a glitch or data corruption, PCA9848 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. Power-on reset is shown in Figure 11. Table 6 specifies the performance of the power-on reset feature for PCA9848 for both types of power-on reset. [1] Level that VDD2 can glitch down to with a ramp rate = 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1 s. [2] Glitch width that will not cause a functional disruption when V DD(gl) =0.5 VDD2. Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 12 and Table 6 provide more information on how to measure these specifications. Fig 11. VDD2 is lowered below the POR threshold, then ramped back up to VDD2 aaa-014361 VDD2 time ramp-down (dV/dt)f ramp-up (dV/dt)r time to re-ramp when VDD2 drops to VPOR(min) − 50 mV or below 0.2 V to VSS td(rst) VI drops below POR levels Table 6. Recommended supply sequencing and ramp rates Tamb =25 C (unless otherwise noted). Not tested; specified by design. Symbol Parameter Condition Min Typ Max Unit (dV/dt)f fall rate of change of voltage Figure 11 0.1 - 2000 ms (dV/dt)r rise rate of change of voltage Figure 11 0.1 - 2000 ms td(rst) reset delay time Figure 11; re-ramp time when VDD2 drops to VPOR(min) 50 mV) or below 0.2 V to VSS 1- - s V DD(gl) glitch supply voltage difference Figure 12 [1] -- 1.0 V tw(gl)VDD supply voltage glitch pulse width Figure 12 [2] -- 10 s VPOR(trip) power-on reset trip voltage falling VDD2 0.7 - - V rising VDD2 -- 1.5 V |
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