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MMA9555L Datasheet(PDF) 7 Page - NXP Semiconductors

Part # MMA9555L
Description  MMA9555L Intelligent Motion- Sensing Pedometer
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMA9555L Datasheet(HTML) 7 Page - NXP Semiconductors

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Functional Overview
MMA9555L Intelligent Pedometer Data Sheet, Rev. 2.2
© NXP B.V. 2016. All rights reserved.
7
2
General Description
2.1
Functional Overview
The MMA9555L is an intelligent motion sensing pedometer, it consists of a 3-axis, MEMS accelerometer and a mixed-signal ASIC
with an integrated, 32-bit CPU. The mixed-signal ASIC can be utilized to measure and condition the outputs of the MEMS accel-
erometer, internal temperature sensor, or a differential analog signal from an external device.
The calibrated, measured sensor outputs can be read via the slave I2C or SPI port and utilized internally within the MMA9555L
to provide advanced intelligent motion detection outputs like pedometer step count, activity level and six directional orientation
detections which can be accessed via the slave I2C or SPI port.
Figure 1. MMA9555L block diagram
A block-level view is shown in Figure 1 with building blocks of devices and built-in applications summarized at a high level. The
analog/mixed-mode subsystem associated with a digital engine is composed of:
The analog subsystem is composed of:
• A 3-axis transducer that is an entirely passive block including the MEMS structures.
• An Analog Front End (AFE) with the following:
– A capacitance-to-voltage converter
– An analog-to-digital converter
– A temperature sensor
The digital subsystem is composed of:
• A 32-bit CPU
• Memory: RAM, ROM, and flash
• Rapid GPIO (RGPIO) port-control logic
Analog Front End (AFE)
BDM
INTC
DBG
Flash
ROM
RAM
I
2C Master
X
axis
C to V
ADC
Temp
Sensor
I
2C slave
SPI slave
Control
and
mailbox
CLKGEN
Two-channel, 16-bit
Timer / PWM module
16-bit
Modulo timer module
Programmable
delay block
INT_O
Y
axis
Z
axis
VDD
VSS
RESET
VSS
VDDA
VSSA
SCL0/RGPIC0/SCLK
SDA0/RGPIO1/SDI
RGPIO2/SCL1/SDO
RGPIO3/SDA1/SSB
RGPIO4/INT
RGPIO5/PDB_A/INT_O
RGPIO6/AN0/TPMCH0
RGPIO7/AN1/TPMCH1
RGPIO8/PDB_B
BKGD/MS/RPGPIO9
AN0
AN1
TPMCH0
TPMCH1
SCL1
SDA1
PDB_A
PDB_B
SCLK
SDI
SDO
SSB
SCL0
SDA0
BKGD
INT
32 bit CPU


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