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30034-23 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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30034-23 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 244 page  www.national.com 8 Revision 3.1 1.0 Architecture Overview The National Semiconductor Geode GXm processor is an x86-compatible 32-bit microprocessor. The decoupled load/store unit (within the memory management unit) allows multiple instructions in a single clock cycle. Other features include single-cycle execution, single-cycle instruction decode, 16 KB write-back cache, and clock ratesupto266 MHz. Thesefeatures aremadepossible by the use of advanced-process technologies and super- pipelining. The GXm processor has low power consumption at all clock frequencies. Where additional power savings are required, designers can make use of Suspend mode, Stop Clock capability, and System Management Mode (SMM). The GXm processor is divided into major functional blocks (as shown in Figure 1-1): • Integer Unit • Floating Point Unit (FPU) • Write-Back Cache Unit • Memory Management Unit (MMU) • Internal Bus Interface Unit • Integrated Functions Instructions are executed in the integer unit and in the floating point unit. The cache unit stores the most recently used data and instructions and provides fast access to this information for the integer and floating point units. 1.1 INTEGER UNIT The integer unit consists of: • Instruction Buffer • Instruction Fetch • Instruction Decoder and Execution The superpipelined integer unit fetches, decodes, and executes x86 instructions through the use of a six-stage integer pipeline. The instruction fetch pipeline stage generates, from the on-chip cache, a continuous high-speed instruction stream for use by the processor. Up to 128 bits of code are read during a single clock cycle. Branch prediction logic within the prefetch unit generates a predicted target address for unconditional or conditional branch instructions. When a branch instruction is detected, the instruction fetch stage starts loading instruc- tions at the predicted address within a single clock cycle. Up to 48 bytes of code are queued prior to the instruction decode stage. The instruction decode stage evaluates the code stream provided by the instruction fetch stage and determines the number of bytes in each instruction and the instruction type. Instructions are processed and decoded at a maxi- mum rate of one instruction per clock. The address calculation function is super-pipelined and contains two stages, AC1 and AC2. If the instruction refers to a memory operand, AC1 calculates a linear memory address for the instruction. The AC2 stage performs any required memory manage- ment functions, cache accesses, and register file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the floating point unit for processing. The execution stage, under control of microcode, exe- cutes instructions using the operands provided by the address calculation stage. Write-back, the last stage of the integer unit, updates the register file within the integer unit or writes to the load/store unit within the memory management unit. Figure 1-1. Internal Block Diagram Write-Back Unit FPU Internal Bus Interface Unit Graphics Memory Display PCI SDRAM Port CS5530 PCI Bus Integer Cache Unit Integrated Functions MMU (CRT/LCD TFT) X-Bus Pipeline Controller Controller Controller C-Bus |
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