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N1077A Datasheet(PDF) 5 Page - Keysight Technologies |
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N1077A Datasheet(HTML) 5 Page - Keysight Technologies |
5 / 19 page 05 | Keysight | Electrical and Optical Clock Data Recovery Solutions - Data Sheet N1077A Optical/Electrical Clock Recovery - Option SMS The N1077A provides instrument-grade clock recovery on electrical and optical signals from 50 MBaud up to 32 GBaud (32.8 GBaud characteristic). Option SMS integrates an optical splitter, hybrid coupler, and amplified O/E to minimize external cabling and losses, while maximizing flexibility and ease-of-use. Just like the N1076A, the N1077A is controlled via a USB connection to an 86100D DCA-X mainframe, or to a standalone PC running N1010A FlexDCA software. Figure 7. As this block diagram shows, the N1077A with Option SMS combines an integrated optical deck (a splitter, bulk-optics coupler, and an amplified O/E) with an instrument-grade electrical clock recovery circuit. Figure 6. The N1077A recovers clock from both electrical and 850 to 1550 nm optical signals operating from 50 MBaud to 32 GBaud. Accurate, convenient solution for recovering clock signals from high-speed optical communication signals – Recovers clock from data streams up to 32 GBaud (Option 232) and 16 GBaud (Option 216) – Supports both NRZ and PAM4 signal types – Provides an easy method for using the electrical clock recovery solution with optical signals – Integrated splitter/coupler extracts a portion of the optical test signal using a built-in coupler. Main optical signal returned to the front panel – Converts the tapped optical signal to an electrical signal using an amplified O/E for greater sensitivity – Operates with both multimode and single-mode optical signals Optical OUT (50 μm/125 μm) Optical IN (50 μm/125 μm) Optical IN (9 μm/125 μm) Optical IOUT (9 μm/125 μm) Optical deck (Option SMS) Electrical clock recovery (refer to N1076A block diagram) Amp O/E Hybrid coupler 70% 30% 70/30 50/50 SM splitter Electrical Data OUT (2.92 mm) Electrical Data IN + – Recovered clock output Auxiliary clock output (4 to 8 GHz) Electrical clock recovery block diagram Loop bandwidth adjustment Ultra-low jitter clock Amp VIG (VCO) Amp Sum Phase detector Frequency divider Front panel divider Peaking adjustment Step generator ADC (for jitter spectrum analysis, JSA) Limit amp |
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