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QL8025 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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QL8025 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 49 page  4XLFN/RJLF &RUSRUDWLRQ ZZZTXLFNORJLFFRP (FOLSVH,,)DPLO\ 'DWD 6KHHW 5HY % Preliminary 3URJUDPPDEOH/RJLF$UFKLWHFWXUDO2YHUYLHZ The Eclipse-II logic cell structure is presented in )LJXUH . This architectural feature addresses today's register-intensive designs. The Eclipse-II logic cell structure presented in )LJXUH is a dual register, multiplexor-based logic cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: 7KH LQSXW 33 LV QRW DQ LQSXW LQ WKH FODVVLFDO VHQVH ,W LV D VWDWLF LQSXW WR WKH ORJLF FHOO DQG VHOHFWVZKLFK SDWK 1= RU 36 LV XVHG DV DQ LQSXW WR WKH 4= UHJLVWHU $OO RWKHU LQSXWV DUH G\QDPLFDQG FDQ EH FRQQHFWHG WRPXOWLSOH URXWLQJ FKDQQHOV The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two- to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. 7DEOH 3HUIRUPDQFH 6WDQGDUGV )XQFWLRQ 'HVFULSWLRQ 6ORZHVW6SHHG *UDGH )DVWHVW6SHHG *UDGH Multiplexer 16:1 5 ns 2.8 ns Parity Tree 24 6 ns 3.4 ns Counter 36 6 ns 3.4 ns 16 bit 250 MHz 450 MHz 32 bit 250 MHz 450 MHz FIFO 128 x 32 155 MHz 280 MHz 256 x 16 155 MHz 280 MHz 128 x 64 155 MHz 280 MHz Clock-to-Out 4.5 ns 2.5 ns System clock 200 MHz 400 MHz |
Similar Part No. - QL8025 |
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Similar Description - QL8025 |
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