50

Ω Low-Voltage, Quad SPST/Dual SPDT Analog

Switches in UCSP

10

______________________________________________________________________________________

Test Circuits/Timing Diagrams (continued)

50%

LOGIC

INPUT

300

Ω

IN_

(

)

0

NO_

OR NC_

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

V+

COM_

35pF

V+

MAX4747–

MAX4750

GND

Figure 2. Switching Time

50%

0

LOGIC

INPUT

SWITCH

OUTPUT 2

0

LOGIC

INPUT

300

Ω

GND

NC_

IN_

IN_

NO_

V+

V+

35pF

300

Ω

35pF

COM_

COM_

SWITCH

OUTPUT 1

MAX4749

Figure 3. Break-Before-Make Interval

GND

COM

1nF

V+

IN

OFF

ON

OFF

Q = (

NC_

OR NO_

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

V+

IN_

MAX4747–

MAX4750

Figure 4. Charge Injection