DDR SDRAM

256MB, 512MB Unbuffered DIMM

Rev. 1.1 August. 2003

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Ordering Information

Operating Frequencies

Part Number

Density

Organization

Component Composition

Height

M368L3223ETN-C(L)B3/AA/A2/B0

256MB

32M x 64

32Mx8 (K4H560838E) * 8EA

1,250mil

M381L3223ETM-C(L)B3/AA/A2/B0

256MB

32M x 72

32Mx8 (K4H560838E) * 9EA

1,250mil

M368L6423ETN-C(L)B3/AA/A2/B0

512MB

64M x 64

32Mx8 (K4H560838E) * 16EA

1,250mil

M381L6423ETM-C(L)B3/AA/A2/B0

512MB

64M x 72

32Mx8 (K4H560838E) * 18EA

1,250mil

B3(DDR333@CL=2.5)

AA(DDR266@CL=2)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Speed @CL2

133MHz

133MHz

133MHz

100MHz

Speed @CL2.5

166MHz

133MHz

133MHz

133MHz

CL-tRCD-tRP

2.5-3-3

2-2-2

2-3-3

2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil), single (256MB), double (512MB) sided

184Pin Unbuffered DIMM based on 256Mb E-die (x8,)