Single/Dual/Quad, Micropower, Single-Supply,

Rail-to-Rail Op Amps

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Detailed Description

The single MAX4091, dual MAX4092 and quad

MAX4094 op amps combine excellent DC accuracy

with rail-to-rail operation at both input and output. With

their precision performance, wide dynamic range at low

supply voltages, and very low supply current, these op

amps are ideal for battery-operated equipment, indus-

trial, and data acquisition and control applications.

Applications Information

Rail-to-Rail Inputs and Outputs

The MAX4091/MAX4092/MAX4094’s input common-

mode range extends 50mV beyond the positive and

negative supply rails, with excellent common-mode

rejection. Beyond the specified common-mode range,

the outputs are guaranteed not to undergo phase

reversal or latchup. Therefore, the MAX4091/MAX4092/

MAX4094 can be used in applications with common-

mode signals, at or even beyond the supplies, without

the problems associated with typical op amps.

The MAX4091/MAX4092/MAX4094’s output voltage

swings to within 15mV of the supplies with a 100k

Ω

load. This rail-to-rail swing at the input and the output

substantially increases the dynamic range, especially

in low-supply-voltage applications. Figure 1 shows the

input and output waveforms for the MAX4092, config-

ured as a unity-gain noninverting buffer operating from

sinusoid centered at 1.5V. The output amplitude is

Input Offset Voltage

Rail-to-rail common-mode swing at the input is obtained

by two complementary input stages in parallel, which

feed a folded cascaded stage. The PNP stage is active

for input voltages close to the negative rail, and the NPN

stage is active for input voltages close to the positive rail.

The offsets of the two pairs are trimmed. However,

there is some residual mismatch between them. This

mismatch results in a two-level input offset characteris-

tic, with a transition region between the levels occurring

at a common-mode voltage of approximately 1.3V

tion region has been widened to approximately 600mV

in order to minimize the slight degradation in CMRR

caused by this mismatch.

The input bias currents of the MAX4091/MAX4092/

MAX4094 are typically less than 20nA. The bias current

flows into the device when the NPN input stage is

active, and it flows out when the PNP input stage is

active. To reduce the offset error caused by input bias

current flowing through external source resistances,

match the effective resistance seen at each input.

Connect resistor R3 between the noninverting input and

ground when using the op amp in an inverting configu-

ration (Figure 2a); connect resistor R3 between the

noninverting input and the input signal when using the

op amp in a noninverting configuration (Figure 2b).

Select R3 to equal the parallel combination of R1 and

R2. High source resistances will degrade noise perfor-

mance, due to the the input current noise (which is mul-

tiplied by the source resistance).

Input Stage Protection Circuitry

The MAX4091/MAX4092/MAX4094 include internal pro-

tection circuitry that prevents damage to the precision

input stage from large differential input voltages. This

protection circuitry consists of back-to-back diodes

between IN+ and IN- with two 1.7k

Ω resistors in series

(Figure 3). The diodes limit the differential voltage

applied to the amplifiers’ internal circuitry to no more

(about 0.7V at +25°C).

Input bias current for the ICs (±20nA) is specified for

small differential input voltages. For large differential

increases the input current at IN+ and IN-:

Output Loading and Stability

Even with their low quiescent current of less than

130µA per op amp, the MAX4091/MAX4092/MAX4094

are well suited for driving loads up to 1k

Ω while main-

taining DC accuracy. Stability while driving heavy

capacitive loads is another key advantage over compa-

rable CMOS rail-to-rail op amps.

In op amp circuits, driving large capacitive loads

increases the likelihood of oscillation. This is especially

true for circuits with high-loop gains, such as a unity-

gain voltage follower. The output impedance and a

capacitive load form an RC network that adds a pole to

the loop response and induces phase lag. If the pole

frequency is low enough—as when driving a large

capacitive load––the circuit phase margin is degraded,

leading to either an under-damped pulse response or

oscillation.

The MAX4091/MAX4092/MAX4094 can drive capacitive

loads in excess of 2000pF under certain conditions

(Figure 4). When driving capacitive loads, the greatest

potential for instability occurs when the op amp is

sourcing approximately 200µA. Even in this case, sta-

bility is maintained with up to 400pF of output capaci-

INPUT CURRENT

VV

V

k

IN

IN

F

=

−−

+−

[(

)

(

)]

.

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✕

Ω