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LM5025SDX Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LM5025SDX Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 16 page Detailed Operating Description The LM5025 PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp Reset technique. The device can be configured to control either a P-Channel clamp switch or an N-Channel clamp switch. With the active clamp technique higher effi- ciencies and greater power densities can be realized com- pared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp output can be configured for either a guaranteed overlap time (for P-Channel switch applications) or a guaranteed dead time (for N_Channel applications). The two internal compound gate drivers paral- lel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high- speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns. The LM5025 includes a high-voltage start-up regulator that operates over a wide input range of 13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync capa- bility, precision reference and thermal shutdown. High Voltage Start-Up Regulator The LM5025 contains an internal high voltage start-up regu- lator that allows the input pin (V IN) to be connected directly to the line voltage. The regulator output is internally current limited to 20mA. When power is applied, the regulator is enabled and sources current into an external capacitor con- nected to the V CC pin. The recommended capacitance range for the V CC regulator is 0.1µF to 100µF. When the voltage on the V CC pin reaches the regulation point of 7.6V and the internal voltage reference (REF) reaches its regulation point of 5V, the controller outputs are enabled. The outputs will remain enabled until V CC falls below 6.2V or the line Under Voltage Lock Out detector indicates that V IN is out of range. In typical applications, an auxiliary transformer winding is connected through a diode to the V CC pin. This winding must raise the V CC voltage above 8V to shut off the internal start-up regulator. Powering V CC from an auxiliary winding improves efficiency while reducing the controller power dis- sipation. The external V CC capacitor must be sized such that the capacitor and V CC self-bias will maintain a VCC voltage greater than 6.2V during the initial start-up. During a fault mode when the converter auxiliary winding is inactive, exter- nal current draw on the V CC line should be limited so the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller. An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by connecting the V CC and the VIN pins together and feeding the external bias voltage into the two pins. Line Under-Voltage Detector The LM5025 contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from Vin to GND, sets the operational range of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 2.5V when Vin is in the desired operating range. If the undervoltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20uA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5V threshold, the current source is turned off causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable / disable function. Pulling the UVLO pin below the 2.5V threshold disables the converter. PWM Outputs The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific applica- tion. For active clamp configurations utilizing a ground refer- enced P-Channel clamp switch, the two outputs should be in phase with the active clamp output overlapping the main output. For active clamp configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the LM5025 is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate driver outputs. The overlap / deadtime magnitude is con- trolled by the resistor value connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for overlap con- trol. The internal configuration detector senses the connec- tion and configures the phase relationship of the main and active clamp outputs. The magnitude of the overlap/dead time can be calculated as follows: Overlap Time (ns) = 2.8 x R SET - 1.2 Dead Time (ns) = 2.9 x R SET +20 R SET in k Ω, Time in ns www.national.com 10 |
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