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K6X8008C2B-TQ55 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6X8008C2B-TQ55 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page K6X8008C2B Family Revision 1.0 September 2003 5 CMOS SRAM CL1) 1.Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=50pF+1TTL DATA RETENTION CHARACTERISTICS 1. CS1 ≥Vcc-0.2V,CS2 ≥Vcc-0.2V(CS1 controlled) or CS2≥Vcc-0.2V(CS2 controlled). Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS1 ≥Vcc-0.2V1) 2.0 - 5.5 V Data retention current IDR Vcc=3.0V, CS1 ≥Vcc-0.2V1) K6X8008C2B-B - - 15 µA K6X8008C2B-F 15 K6X8008C2B-Q 30 Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial product: TA=0 to 70 °C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C) Parameter List Symbol Speed Bins Units 55ns 70ns Min Max Min Max Read Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Select to Output tCO - 55 - 70 ns Output Enable to Valid Output tOE - 25 - 35 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 20 0 25 ns Output Disable to High-Z Output tOHZ 0 20 0 25 ns Output Hold from Address Change tOH 10 - 10 - ns Write Write Cycle Time tWC 55 - 70 - ns Chip Select to End of Write tCW 45 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - ns Write Pulse Width tWP 40 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 20 0 20 ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns |
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