IDT72V255LA20PFI datasheet(2/27 Pages) IDT

Part #	IDT72V255LA20PFI

Description	3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18

Download	27 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

Logo

2 / 27 page

2

IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN CONFIGURATIONS

TQFP (PN64-1, ORDER CODE: PF)

STQFP (PP64-1, ORDER CODE: TF)

TOP VIEW

DESCRIPTION (CONTINUED)

PIN 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

WEN

SEN

DC(1)

VCC

GND

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

VCC

Q13

Q12

Q11

GND

Q10

Q9

Q8

Q7

Q6

GND

4672 drw 02

••••• The period required by the retransmit operation is now fixed and short.

••••• The first word data latency period, from the time the first word is written to

anemptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previous SuperSync devices has been eliminated on this SuperSync

family.)

SuperSync FIFOs are particularly appropriate for networking, video,

telecommunications,datacommunicationsandotherapplicationsthatneedto

buffer large amounts of data.

TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable

(

WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen

WEN is asserted. The output port is controlled by a Read Clock (RCLK) input

and Read Enable (

REN) input. Data is read from the FIFO on every rising

edgeofRCLKwhen

RENisasserted. AnOutputEnable(OE)inputisprovided

for three-state control of the outputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

to fMAX with complete independence. There are no restrictions on the

frequency of one clock input with respect to the other.

NOTE:

1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.

Similar Part No. - IDT72V255LA20PFI

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72V255LA	366Kb / 27P	3.3 VOLT CMOS SuperSync FIFO
Integrated Device Techn...	IDT72V255LA	366Kb / 27P	3.3 VOLT CMOS SuperSync FIFO

More results

Similar Description - IDT72V255LA20PFI

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	72V255LA	402Kb / 28P	3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 JANUARY 2018
Renesas Technology Corp	IDT72255LA	404Kb / 28P	CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 NOVEMBER 2017
Integrated Device Techn...	IDT72255	394Kb / 30P	CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18
Renesas Technology Corp	72V275	553Kb / 26P	3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18 FEBRUARY 2018
Integrated Device Techn...	IDT72V295	237Kb / 26P	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 131,072 x 18 262,144 x 18
Renesas Technology Corp	72V295	391Kb / 27P	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 131,072 x 18 262,144 x 18 MARCH 2018
Renesas Technology Corp	72V261LA	395Kb / 28P	3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 32,768 x 9 FEBRUARY 2018
Integrated Device Techn...	IDT72264	392Kb / 31P	VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9
	IDT72V271	310Kb / 27P	3.3 VOLT CMOS SuperSync FIFO
	IDT72V285	213Kb / 25P	3.3 VOLT CMOS SuperSync FIFO

More results

IDT72V255LA20PFI Datasheet(PDF) 2 Page - Integrated Device Technology

IDT72V255LA20PFI Datasheet(HTML) 2 Page - Integrated Device Technology

Similar Part No. - IDT72V255LA20PFI

Similar Description - IDT72V255LA20PFI

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL