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IDT709089SL Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT709089SL Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  ©2000 Integrated Device Technology, Inc. FEBRUARY 2000 DSC-3242/10 1 Functional Block Diagram Features: x True Dual-Ported memory cells which allow simultaneous access of the same memory location x High-speed clock to data access – Commercial: 9/12/15ns (max.) x Low-power operation – IDT709089S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709089L Active: 950mW (typ.) Standby: 1mW (typ.) x Flow-Through or Pipelined output mode on either port via the FT/PIPE pin x Counter enable and reset features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66MHz operation in the Pipelined output mode x TTL- compatible, single 5V (±10%) power supply x Industrial temperature range (–40°C to +85°C) is available for selected speeds x Available in 100-pin Thin Quad Flatpack (TQFP) package HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM PRELIMINARY IDT709089S/L 0 1 0/1 1 0/1 0 R/ WR OER CE0R CE1R FT/PIPER I/O Control MEMORY ARRAY Counter/ Address Reg. I/O Control 3242 drw 01 A15R A0R CLKR ADSR CNTENR CNTRSTR A0L CLKL ADSL A15L CNTENL CNTRSTL Counter/ Address Reg. R/ WL CE0L OEL CE1L I/O0L - I/O7L I/O0R -I/O7R 1 0/1 0 0 1 0/1 FT/PIPEL |
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