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INDUSTRIALTEMPERATURERANGE

IDT5V2528/A

2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER

JUNE 2003

2002

Integrated Device Technology, Inc.

DSC 5971/11

c

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 1:10 fanout

• 3-level inputs for output control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Configurable 2.5V or 3.3V LVTTL outputs

• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps

• Spread spectrum compatible

• Operating Frequency:

−−−−−

Std: 25MHz to 140MHz

−−−−− A: 25MHz to 167MHz

• Available in TSSOP package

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock

loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency

and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

IDT5V2528/A

2.5V / 3.3V PHASE-LOCK

LOOP CLOCK DRIVER

ZERO DELAY BUFFER

19

PLL

3

24

17

16

26

13

10

20

12

6

7

5

FBIN

CLK

G_Ctrl

28

22

T_Ctrl

1

MODE

SELECT

One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of

the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL

outputs. The number of 2.5V outputs is controlled by 3-level input signals

3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.

Outputsignaldutycyclesareadjustedto50percent,independentoftheduty

cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.

When the G_Ctrl input is mid or high, the outputs switch in phase and

disabled to the logic-low state.

Unlike many products containing PLLs, the IDT5V2528 does not require

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the IDT5V2528 requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as

following any changes to the PLL reference or feedback signals. The PLL