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HT95A200 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc |
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HT95A200 Datasheet(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 48 page  HT95AXXX Rev. 1.20 8 May 26, 2004 ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read in- struction used in the ISR. Errors will then occur. Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be dis- abled prior to the table read instruction. It will not be en- abled until the TBLH has been backed-up. All table related instructions require two cycles to complete the operation. These areas may function as normal pro- gram memory depending on the requirements. Stack Register This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 12 levels (HT95A400/40P), 8 lev- els (HT95A300/30P, HT95A200/20P) or 4 levels (HT95A100/10P) and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writable.Ata subroutine call or interrupt acknowledge signal, the con- tents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, sig- naled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and an interrupt takes place, the inter- rupt request flag will be recorded but the acknowledge signal will be inhibited even if this interrupt is enabled. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature pre- vents stack overflow allowing the programmer to use the structure more easily. If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 12, 8 or 4, de- pending on various MCU type, returned addresses are stored). Data Memory The data memory is divided into three functional groups: special function registers, embedded control register and general purpose memory. Most are read/write, but some are read only. The special function registers are located from 00H to 1FH. The embedded control registers are located in the memory areas from 20H to 3FH. The remaining spaces which are not specified in the following table before the 40H are reserved for future expanded usage and read- ing these locations will get ²00H². The general purpose data memory is divided into 15 banks (HT95A400/40P), 11 banks (HT95A300/30P), 6 banks (HT95A200/20P) or 2 banks (HT95A100/10P). The banks in the RAM are all addressed from 40H to 0FFH and they are selected by setting the value of the Bank Pointer (BP). All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1). The bank1~bank14 are only indirectly accessible through memory pointer 1 register (MP1). HT95A400/40P Instruction(s) Table Location *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 111111 @7 @6 @5 @4 @3 @2 @1 @0 HT95A300/30P Instruction(s) Table Location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 11111 @7 @6 @5 @4 @3 @2 @1 @0 HT95A200/20P, HT95A100/10P Instruction(s) Table Location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1111 @7 @6 @5 @4 @3 @2 @1 @0 Note: *13~*0: Table location bits #7~#0: TBHP register bit7~bit0 @7~@0: TBLP register bit7~bit0 P12~P8: Current program counter bits |
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