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DAC8534 Datasheet(PDF) 3 Page - Texas Instruments |
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DAC8534 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 20 page  3 DAC8534 SBAS254D www.ti.com REFERENCE INPUT Reference Current VREF = AVDD = +5V 135 180 µA VREF = AVDD = +3V 80 120 µA Reference Input Range 0 AVDD V Reference Input Impedance 37 k Ω LOGIC INPUTS (2) Input Current ±1 µA V INL, Input LOW Voltage IOV DD = +5V 0.8 V V INL, Input LOW Voltage IOV DD = +3V 0.6 V V INH, Input HIGH Voltage IOV DD = +5V 2.4 V V INH, Input HIGH Voltage IOV DD = +3V 2.1 V Pin Capacitance 3pF POWER REQUIREMENTS AV DD 2.7 5.5 V IOV DD 2.7 5.5 V AIDD (normal mode) DAC Active and Excluding Load Current IOIDD 10 20 µA AI DD = +3.6V to +5.5V V IH = IOVDD and VIL = GND 0.95 1.6 mA AI DD = +2.7V to +3.6V V IH = IOVDD and VIL = GND 0.9 1.5 mA AI DD (all power-down modes) AI DD = +3.6V to +5.5V V IH = IOVDD and VIL = GND 0.8 1 µA AI DD = +2.7V to +3.6V V IH = IOVDD and VIL = GND 0.05 1 µA POWER EFFICIENCY IOUT/IDD ILOAD = 2mA, AVDD = +5V 89 % TEMPERATURE RANGE Specified Performance –40 +105 °C PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) AV DD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified. DAC8534 NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. PIN NAME DESCRIPTION 1VOUTA Analog output voltage from DAC A. 2VOUTB Analog output voltage from DAC B. 2VREFH Positive reference voltage input. 4AVDD Power supply input, +2.7V to +5.5V. 5VREFL Negative reference voltage input. 6 GND Ground reference point for all circuitry on the part. 7VOUTC Analog output voltage from DAC C. 8VOUTD Analog output voltage from DAC D. 9 SYNC Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8534). 10 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. 11 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. 12 IOVDD Digital Input-Output Power Supply 13 A0 Address 0 — sets device address, see Table II. 14 A1 Address 1 — sets device address, see Table II. 15 ENABLE Active LOW, ENABLE LOW connects the SPI inter- face to the serial port. 16 LDAC Load DACs, rising edge triggered loads all DAC registers. PIN DESCRIPTIONS PIN CONFIGURATION Top View TSSOP V OUTA V OUTB V REFH AV DD V REFL GND V OUTC V OUTD LDAC ENABLE A1 A0 IOV DD D IN SCLK SYNC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DAC8534 |
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