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CS8952T-IQ Datasheet(PDF) 11 Page - Cirrus Logic |
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CS8952T-IQ Datasheet(HTML) 11 Page - Cirrus Logic |
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11 / 86 page  DS206TPP2 11 CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver CIRRUS LOGIC ADVANCED PRODUCT DATABOOK AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57. These three-level input pins are sampled during power-up or reset. They control the forced or advertised auto-negotiation operating modes. If either of these pins is left unconnected, internal logic pulls its signal to a mid-range value, designated as 'M' in the following table. Either pin may also be connected to a 5 to 25 MHz TTL-level clock source, designated as ’C’ in the following table. A minimum of 8 rising edges of the clock are required while RESET is asserted for the AN[1:0] input logic to interpret the input as ’C’. Auto-Negotiation may also be enabled and the advertised capabilities modified under software control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and 10 of the Auto-Negotiation Advertisement Register (address 04h). These pins are pulled to ‘M’ through weak internal resistors (> 150 K Ω). Other values may be set by tying them directly to VDD_MII, VSS, or a clock source, or through external 10 K Ω pull-up or pull-down resistors. BP4B5B - Bypass 4B5B Coders. Input, Pin 56. When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). AN1 pin AN0 pin Forced/Auto Speed Full/Half Duplex 0 M Forced 10 Mb/s Half 1 M Forced 10 Mb/s Full M 0 Forced 100 Mb/s Half M 1 Forced 100 Mb/s Full C M Forced 100 Mb/s Full (Note 1) 1. The Auto-Negotiation Advertisement Register will be modified to advertise 100 Mb/s Full/Half. M C Forced 100 Mb/s Full (Note 2) 2. The Auto-Negotiation Advertisement Register will be modified to advertise 100/10 Mb/s Full. C C Forced 100 Mb/s Half (Note 3) 3. The Auto-Negotiation Advertisement Register will be modified to advertise 100/10 Mb/s Half. M M Auto-Neg 100/10 Mb/s Full/Half 0 0 Auto-Neg 10 Mb/s Half 0 1 Auto-Neg 10 Mb/s Full 1 0 Auto-Neg 100 Mb/s Half 1 1 Auto-Neg 100 Mb/s Full C 1 Auto-Neg 100/10 Mb/s Full C 0 Auto-Neg 100/10 Mb/s Half 1 C Auto-Neg 100 Mb/s Full/Half 0 C Auto-Neg 10 Mb/s Full/Half |
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Similar Description - CS8952T-IQ |
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