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CDCR83 Datasheet(PDF) 8 Page - Texas Instruments |
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CDCR83 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 13 page  CDCR83 DIRECT RAMBUS CLOCK GENERATOR SCAS632A – APRIL 2001 – REVISED MARCH 2002 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 state transition latency specifications (continued) PARAMETER FROM TO TEST CONDITIONS MIN TYP† MAX UNIT t(powerdown) Delay time, PWRDNB ↓ to the device in the power-down mode Normal Powerdown See Figure 8 1 ms t(STOP) Maximum time in CLKSTOP (STOPB = 0) before reentering normal mode (STOPB = 1) STOPB Normal See Figure 10 100 µs t(ON) Minimum time in normal mode (STOPB = 1) before reentering CLKSTOP (STOPB = 0) Normal CLK stop See Figure 10 100 ms t(DISTLOCK) Time from when CLK/CLKB output is settled to when the phase error between SYNCLKN and PCLKM falls within t(phase) Unlocked Locked 5 ms † All typical values are at VDD = 3.3 V, TA = 25°C. |
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