Si3402B-EVB

Rev. 1.1

11

d. Keep the circular area of the loop from the Switcher FET output to the inductor or transformer and

returning from the input filter capacitors (C1–C4) to Vss2 as small a diameter as possible. Also, minimize

the circular area of the loop from the output of the inductor or transformer to the Schottky diode and

returning through the first stage output filter capacitor back to the inductor or transformer as small as

possible. If possible, keep the direction of current flow in these two loops the same.

e. Keep the high power traces as short as possible.

f.

Keep the feedback and loop stability components as far from the transformer/inductor and noisy power

traces as possible.

g. If the outputs have a ground plane or positive output plane, do not connect the high current carrying

components and the filter capacitors through the plane. Connect them together, and then connect to the

plane at a single point.

h. As a convenience in layout, please note that the IC is symmetrical with respect to CT1, CT2, SP1, and

SP2. These leads can be interchanged. At least one pair of CT1/CT2 or SP1/SP2 should be connected.

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