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NCV8177AMX250TCG Datasheet(PDF) 9 Page - ON Semiconductor |
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NCV8177AMX250TCG Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 11 page NCV8177 www.onsemi.com 9 The EN pin has internal pull−down current source with value of 300 nA typ. which assures the device is turned off when the EN pin is unconnected. In case when the EN function isn’t required the EN pin should be tied directly to IN pin. Output Current Limit Output current is internally limited to a 750 mA typ. The LDO will source this current when the output voltage drops down from the nominal output voltage (test condition is VOUT−NOM – 100 mV). If the output voltage is shorted to ground, the short circuit protection will limit the output current to 700 mA typ. The current limit and short circuit protection will work properly over the whole temperature and input voltage ranges. There is no limitation for the short circuit duration. Thermal Shutdown When the LDO’s die temperature exceeds the thermal shutdown threshold value the device is internally disabled. The IC will remain in this state until the die temperature decreases by value called thermal shutdown hysteresis. Once the IC temperature falls this way the LDO is back enabled. The thermal shutdown feature provides the protection against overheating due to some application failure and it is not intended to be used as a normal working function. Power Dissipation Power dissipation caused by voltage drop across the LDO and by the output current flowing through the device needs to be dissipated out from the chip. The maximum power dissipation is dependent on the PCB layout, number of used Cu layers, Cu layers thickness and the ambient temperature. The maximum power dissipation can be computed by following equation: P D(MAX) + T J * TA q JA + 125 * T A q JA [W] (eq. 1) Where: (TJ − TA) is the temperature difference between the junction and ambient temperatures and θJA is the thermal resistance (dependent on the PCB as mentioned above). For reliable operation junction temperature should be limited to +125 °C. The power dissipated by the LDO for given application conditions can be calculated by the next equation: P D + VIN @ IGND ) VIN * VOUT @ IOUT [W] (eq. 2) Where: IGND is the LDO’s ground current, dependent on the output load current. Connecting the exposed pad and N/C pin to a large ground planes helps to dissipate the heat from the chip. The relation of θJA and PD(MAX) to PCB copper area and Cu layer thickness could be seen on the Figure 26. Reverse Current The PMOS pass transistor has an inherent body diode which will be forward biased in the case when VOUT > VIN. Due to this fact in cases, where the extended reverse current condition can be anticipated the device may require additional external protection. Power Supply Rejection Ratio The LDO features very high power supply rejection ratio. The PSRR at higher frequencies (in the range above 100 kHz) can be tuned by the selection of COUT capacitor and proper PCB layout. A simple LC filter could be added to the LDO’s IN pin for further PSRR improvement. Enable Turn−On Time The enable turn−on time is defined as the time from EN assertion to the point in which VOUT will reach 98% of its nominal value. This time is dependent on various application conditions such as VOUT−NOM, COUT and TA. PCB Layout Recommendations To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors as close as possible to the device pins and make the PCB traces wide. In order to minimize the solution size, use 0402 or 0201 capacitors size with appropriate effective capacitance. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated from the equation above (Power Dissipation section). Exposed pad and N/C pin should be tied to the ground plane for good power dissipation. |
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