TPS54810

SLVS420A − MARCH 2002 − R EVISED AUGUST 2002

www.ti.com

9

GROUNDING AND POWERPAD LAYOUT

The TPS54810 has two internal grounds (analog and

power). Inside the TPS54810, the analog ground ties to all

of the noise sensitive signals, while the power ground ties

to the noisier power signals. The PowerPAD must be tied

directly to AGND. Noise injected between the two ground

can

degrade

the

performance

of

the

TPS54810,

particularly at higher output currents. However, ground

noise on an analog ground plane can also cause problems

with some of the control and bias signals. For these

reasons, separate analog and power ground planes are

recommended. These two planes should tie together

directly at the IC to reduce noise between the two grounds.

The only components that should tie directly to the power

ground plane are the input capacitor, the output capacitor,

the input voltage decoupling capacitor, and the PGND pins

of the TPS54810. The layout of the TSP54810 evaluation

module is representative of a recommended layout for a 4

layer board. Documentation for the TPS54810 evaluation

module can be found on the Texas Instruments web site

under the TPS54810 product folder.

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

For operation at full rated load current, the analog ground

plane must provide adequate heat dissipating area. A 3

inch by 3 inch plane of 1 ounce copper is recommended,

though not mandatory, depending on ambient temperature

and airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the top or bottom layers also help dissipate heat, and

any area available should be used when 8 A or greater

operation is desired. Connection from the exposes area of

the PowerPAD to the analog ground plane layer should be

made using 0.013 inch diameter vias to avoid solder

wicking through the vias. Eight vias should be in the

PowerPAD area with four additional vias located under the

device package. The size of the vias under the package,

but not in the exposed thermal pad area, can be increased

to 0.018. Additional vias beyond the twelve recommended

that enhance thermal performance should be included in

areas not under the device package.

Connect Pin 1 to Analog Ground Plane

in This Area For Optimum Performance

Minimum Recommended Top

Side Analog Ground Area

0.3478

0.0150

0.06

0.0256

0.1700

0.1340

0.0630

0.0400

Ø 0.0180

4 PL

0.2090

Ø 0.0130

8 PL

Minimum Recommended Exposed

Copper Area For Powerpad. 5mm

Stencils may Require 10 Percent

Larger Area

0.0650

0.0500

0.0500

0.0650

0.0339

0.0339

0.0500

Minimum Recommended Thermal Vias: 8 x 0.013 diameter Inside

Powerpad Area 4 x 0.018 diameter Under Device as Shown.

Additional 0.018 diameter Vias May be Used if Top Side Analog Ground

Area is Extended.

0.3820

Figure 10. Recommended Land Pattern for 28-Pin PWP PowerPAD