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NCP12510ASN100T1G Datasheet(PDF) 3 Page - ON Semiconductor |
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NCP12510ASN100T1G Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 27 page NCP12510 www.onsemi.com 3 Figure 2. Internal Circuit Architecture 65 / 100 kHz Oscillator Clamp DRV VCC and logic management VCC + VOVP GND OPP/ Latch + Vlatch Up Counter to 4 CS FB VFB(open) Req Kratio Frequency foldback Rramp peak current freeze Soft-start + Vlimit +VOPP VOPP Up counter to 8 Jittering + _ RST tlatch(del) tlatch(blank) tOVP(del) + Vskip S R Q Q Dmax LEB Vlimit + Fault timer OCP Fault RST RST DRV pulse VOPP DRV pulse R S Q Q Error flag DRV pulse DRV pulse Latch / Auto-revery management Note: depend on IC option OVP/OTP Latch VCC(OVP) IC stop DRV stop VCC(OVP) VCC(min) IC start IC stop IC reset OCP Fault OVP/OTP Latch Pre-short Latch / Auto- recovery mode DRV stop Latch / Auto- recovery mode Internal supply Pre-short 1 st DRV pulse during IC start VCC(min) S R Q Q (for OCP &UVLO latched option ) Armed flag IC in regulation FB@gnd IC in regulation VCC(on) |
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