DS90CR283 Pin Description — Channel Link Transmitter

Pin Name

I/O

No.

Description

TxIN

I

28

TTL Level inputs

TxOUT+

O

4

Positive LVDS differential data output

TxOUT−

O

4

Negative LVDS differential data output

TxCLK IN

I

1

TTL level clock input. The rising edge acts as data strobe

TxCLK OUT+

O

1

Positive LVDS differential clock output

TxCLK OUT−

O

1

Negative LVDS differential clock output

PWR DOWN

I

1

TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power

down

V

CC

I

4

Power supply pins for TTL inputs

GND

I

5

Ground pins for TTL inputs

PLL V

CC

I

1

Power supply pin for PLL

PLL GND

I

2

Ground pins for PLL

LVDS V

CC

I

1

Power supply pin for LVDS outputs

LVDS GND

I

3

Ground pins for LVDS outputs

DS90CR284 Pin Description — Channel Link Receiver

Pin Name

I/O

No.

Description

RxIN+

I

4

Positive LVDS differential data inputs

RxIN−

I

4

Negative LVDS differential data inputs

RxOUT

O

28

TTL level outputs

RxCLK IN+

I

1

Positive LVDS differential clock input

RxCLK IN−

I

1

Negative LVDS differential clock input

RxCLK OUT

O

1

TTL level clock output. The rising edge acts as data strobe

PWR DOWN

I

1

TTL level input. Assertion (low input) maintains the receiver outputs in the previous state

V

CC

I

4

Power supply pins for TTL outputs

GND

I

5

Ground pins for TTL outputs

PLL V

CC

I

1

Power supply for PLL

PLL GND

I

2

Ground pin for PLL

LVDS V

CC

I

1

Power supply pin for LVDS inputs

LVDS GND

I

3

Ground pins for LVDS inputs

Applications Information

The Channel Link devices are intended to be used in a wide

variety of data transmission applications. Depending upon

the application the interconnecting media may vary. For ex-

ample, for lower data rate (clock rate) and shorter cable

cal. For higher speed/long distance applications the media’s

performance becomes more critical. Certain cable construc-

tions provide tighter skew (matched electrical length be-

tween the conductors and pairs). Twin-coax for example, has

been demonstrated at distances as great as 5 meters and

with the maximum data transfer of 1.848 Gbit/s. Additional

applications information can be found in the following Na-

tional Interface Application Notes:

AN = ####

Topic

AN-1041

Introduction to Channel Link

AN-1035

PCB Design Guidelines for LVDS and

Link Devices

AN-806

Transmission Line Theory

AN = ####

Topic

AN-905

Transmission Line Calculations and

Differential Impedance

AN-916

Cable Information

CABLES: A cable interface between the transmitter and re-

ceiver needs to support the differential LVDS pairs. The

21-bit CHANNEL LINK chipset (DS90CR213/214) requires

four pairs of signal wires and the 28-bit CHANNEL LINK

chipset (DS90CR283/284) requires five pairs of signal wires.

The ideal cable/connector interface would have a constant

100

Ω differential impedance throughout the path. It is also

MHz clock rate) to maintain a sufficient data sampling win-

dow at the receiver.

In addition to the four or five cable pairs that carry data and

clock, it is recommended to provide at least one additional

conductor (or pair) which connects ground between the

transmitter and receiver. This low impedance ground pro-

vides a common mode return path for the two devices. Some

of the more commonly used cable types for point-to-point ap-

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