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SLK2501IPZP Datasheet(PDF) 10 Page - Texas Instruments |
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SLK2501IPZP Datasheet(HTML) 10 Page - Texas Instruments |
10 / 20 page SLK2501 OC48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER SLLS502A – OCTOBER 2001 – REVISED NOVEMBER 2001 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 jitter tolerance (continued) f0 f1 f2 f3 f4 Frequency – Hz A3 A2 A1 Slope = –20 dB / Decade Slope = –20 dB / Decade OC-N/STS-N LEVEL f0 (Hz) F1 (Hz) F2 (Hz) F3 (kHz) F4 (kHz) A1 (Ulpp) A2 (Ulpp) A3 (Ulpp) 3 10 30 300 6.5 65 0.15 1.5 15 12 10 30 300 25 250 0.15 1.5 15 24 Not specified 48 10 600 6000 100 1000 0.15 1.5 15 Figure 3. Input Jitter Tolerance jitter generation The jitter of a serial clock and serial data outputs must not exceed 0.01 UI rms/0.1 UIp-p when a serial data with no jitter is presented to the inputs. The measurement bandwidth for intrinsic jitter is 12-kHz to 20-MHz. loop timing mode When LOOPTIME is high, the clock synthesizer used to serialize the transmit data is bypassed and the timing is provided by the recovered clock. However, REFCLK is still needed for the recovery loop operation. loss of lock indicator The SLK2501 has a lock detection circuit to monitor the integrity of the data input. When the clock recovery loop is locked to the input serial data stream, the LOL signal goes high. If the recovered clock frequency deviates from the reference clock frequency by more than 100 ppm, LOL goes low. If the data stream clock rate deviates by more than 170 ppm, loss of lock occurs. If the data streams clock rate deviates more than 500 ppm from the local reference clock, the LOL output status might be unstable. Upon power up, the LOL goes low until the PLL is close to phase lock with the local reference clock. loss of signal The loss of signal (LOS) alarm is set high when no transitions appear in the input data path for more than 2.3 µs. The LOS signal becomes active when the above condition occurs. If the serial inputs of the device are ac-coupled to its source, the ac-couple cap needs to be big enough to maintain a signal level above the threshold of the receiver for the 2.3 µs no transition period. Once activated, the LOS alarm pin is latched high until the receiver detects an A1A2 pattern. The recovered clock (RXCLK) is automatically locked to the local reference when LOS occurs. The parallel data (RXDATAx) may still be processed even when LOS is activated. |
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