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NCP81239 Datasheet(PDF) 3 Page - ON Semiconductor |
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NCP81239 Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 19 page NCP81239 www.onsemi.com 3 Figure 3. Block Diagram Startup INPUT UVLO _ + − + Error OTA 500 µS/100µS CO2 BST1 HSG1 VSW1 LSG1 VDRV PGND1 LSG2 VDRV PGND2 BST2 HSG2 VSW2 NOL Drive Logic_2 NOL Drive Logic_1 CSN1 CSP1 CSP2 CSN2 VCC VDRV CS1 CS2 CS1 CS1 CS2 CS2 NC CLIND INT SDA SCL Limit Registers Status Registers I2C Interface Digital Configuration Oscillator Reference INT Interface VFB COMP − + CC RC CP ∑ CS2_INT CS2_INT ∑ CS1_INT CS1_INT 0_Ramp Buck Logic Boost Logic Buck Boost Logic CONFIG CONFIG SW1 SW2 SW3 SW4 VDRV CFET DBIN Current Limiting Circuit For Dead Battery CONFIG VFB PG Thermal Shutdown TS Control Logic SW1 SW2 SW3 SW4 IUVLOB BG IUVLOB PG TS CLIND BG + − CLINDP1 CLIMP1 − + EN 0.8V EN EN TS − + CL2P CL2P REF CS2_INT CL2 CL1 BG Value Register ADC CSP1 CS1_INT CS2_INT Analog Mux AGND FLAG + − CLINDP2 CLIMP2 CLIND VCC EN LOGIC ENPOL EN_MASK − + VFB PG_Low PG_High − + PG VFB PG_MSK OV_REF OV PG/ OV/ LOGIC OV_MSK − + CO VDRV + − CL2N REF CL2N CONFIG CONFIG − + CL1P CL1P REF CS1_INT + − CL1N REF CL1N CONFIG CS1_INT 0_Ramp VDRV PDRV CFET PDRV Q2 V1 + − 4.0V VDRV_rdy + − 4.0V Vcc_rdy + Boot1V Boot1 _UVLO + Boot1V Boot2 _UVLO Q1 V2 DBOUT V1 FB 180_Ramp Ramp_0 Ramp_180 CSP1 CSN2 VFB PDRV CFET Table 1. PIN FUNCTION DESCRIPTION Pin Pin Name Description 1 HSG1 S1 gate drive. Drives the S1 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch node voltage VSW1. 2 LSG1 Drives the gate of the S2 N−channel MOSFET between ground and VDRV. 3, 22 PGND Power ground for the low side MOSFET drivers. Connect these pins closely to the source of the bottom N−channel MOSFETs. 4 CSN1 Negative terminal of the current sense amplifier. 5 CSP1 Positive terminal of the current sense amplifier. 6 V1 Input voltage of the converter 7 CS1 Current sense amplifier output. CS1 will source a current that is proportional to the voltage across RS1 to an external resistor. Ground this pin if not used. 8 CLIND Open drain output to indicate that the CS1 or CS2 voltage has exceeded the I2C programmed limit. 9 SDA I2C interface data line. 10 SCL I2C interface clock line. 11 INT Interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and oth- er I2C programmable functions. 12 CFET Controlled drive of an external MOSFET that connects a bulk output capacitor to the output of the power converter. Necessary to adhere to low capacitance limits of the standard USB Specifications for power prior to USB PD negotiation. 13−14 AGND The ground pin for the analog circuitry. 15 COMP Output of the transconductance amplifier used for stability in closed loop operation. |
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