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GD25LQ128CWIGR Datasheet(PDF) 8 Page - ELM Electronics |
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GD25LQ128CWIGR Datasheet(HTML) 8 Page - ELM Electronics |
8 / 62 page 8 Rev.1.0 62 - http://www.elm-tech.com GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash Figure 1. Hold Condition HOLD HOLD CS# SCLK HOLD# 5. DATA PROTECTION The GD25LQ128C provides the following data protection methods: ♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: - Power-Up - Write Disable (WRDI) - Write Status Register (WRSR) - Page Program (PP) - Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) - Erase Security Registers / Program Security Registers ♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the memory array that can be read but not change. ♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. ♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion × × 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 to 255 FC0000H-FFFFFFH 256KB Upper 1/64 0 0 0 1 0 248 to 255 F80000H-FFFFFFH 512KB Upper 1/32 0 0 0 1 1 240 to 255 F00000H-FFFFFFH 1MB Upper 1/16 0 0 1 0 0 224 to 255 E00000H-FFFFFFH 2MB Upper 1/8 0 0 1 0 1 192 to 255 C00000H-FFFFFFH 4MB Upper 1/4 0 0 1 1 0 128 to 255 800000H-FFFFFFH 8MB Upper 1/2 0 1 0 0 1 0 to 3 000000H-03FFFFH 256KB Lower 1/64 0 1 0 1 0 0 to 7 000000H-07FFFFH 512KB Lower 1/32 0 1 0 1 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/16 0 1 1 0 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/8 0 1 1 0 1 0 to 63 000000H-3FFFFFH 4MB Lower 1/4 0 1 1 1 0 0 to 127 000000H-7FFFFFH 8MB Lower 1/2 Table 1. GD25LQ128C Protected area size (CMP=0) |
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