DS90CR211/DS90CR212

21-Bit Channel Link

General Description

The DS90CR211 transmitter converts 21 bits of CMOS/TTL

data into three LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fourth LVDS link. Every

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. The DS90CR212 receiver converts the

LVDS data streams back into 21 bits of CMOS/TTL data. At

a transmit clock frequency of 40 MHz, 21 bits of TTL data are

transmitted at a rate of 280 Mbps per LVDS data channel.

Using a 40 MHz clock, the data throughput is 840

Mbit/s(105 Mbyte/s).

The multiplexing of the data lines provides a substantial

cable reduction. Long distance parallel single-ended buses

typically require a ground wire per active signal (and have

very limited noise rejection capability). Thus, for a 21-bit wide

data bus and one clock, up to 44 conductors are required.

With the Channel Link chipset as few as 9 conductors (3

data pairs, 1 clock pair and a minimum of one ground) are

needed. This provides a 80% reduction in required cable

width, providing a system cost savings, reduces connector

physical size, and reduces shielding requirements due to the

cables smaller form factor.

The 21 CMOS/TTL inputs can support a variety of signal

combinations. For example, 5 4-bit nibbles plus 1 control, or

2 9-bit (byte + parity) and 3 control.

Features

n Narrow bus reduces cable size and cost

n 290 mV swing LVDS data transmission

n 840 Mbit/s data throughput

n Low swing differential current mode drivers reduce EMI

n Rising edge data strobe

n Power down mode

n Offered in low profile 48-lead TSSOP package

Block Diagrams

DS90CR211

DS012637-27

Order Number DS90CR211MTD

See NS Package Number MTD48

DS90CR212

DS012637-1

Order Number DS90CR212MTD

See NS Package Number MTD48

July 1997

© 1998 National Semiconductor Corporation

DS012637

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