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MB90F562 Datasheet(PDF) 11 Page - Fujitsu Component Limited. |
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MB90F562 Datasheet(HTML) 11 Page - Fujitsu Component Limited. |
11 / 581 page MB90560 series ix FIGURES Figure 1.3-2 Block diagram ..........................................................................................................................5 Figure 1.4-1 Pin assignment of FPT-64P-M09 ............................................................................................6 Figure 1.4-2 Pin assignment of FPT-64P-M09 ............................................................................................7 Figure 1.4-3 Pin assignment of DIP-64P-M01 .............................................................................................8 Figure 1.5-1 Dimensions of FPT-64P-M06 package .................................................................................10 Figure 1.5-2 Dimensions of FPT-64P-M09 package .................................................................................11 Figure 1.5-3 Dimensions of DIP-64P-M01 package ..................................................................................12 Figure 1.8-1 Sample connection of external clock .....................................................................................21 Figure 2.2-1 Sample relationship between the F2MC-16LX system and the memory map ......................26 Figure 2.3-1 Memory maps ........................................................................................................................28 Figure 2.4-1 Linear addressing and bank addressing memory management ...........................................29 Figure 2.4-2 Example of direct specified 24-bit physical address in linear addressing .............................30 Figure 2.4-3 Example of indirect specified address with a 32-bit general-purpose register in linear addressing ...............................................................................................................30 Figure 2.4-4 Sample bank addressing .......................................................................................................33 Figure 2.5-1 Storage of multibyte data in RAM ..........................................................................................34 Figure 2.5-2 Storage of a multibyte operand .............................................................................................34 Figure 2.5-3 Storage of multibyte data in a stack ......................................................................................35 Figure 2.5-4 Multibyte data access on a bank boundary ...........................................................................35 Figure 2.6-1 Dedicated registers and general-purpose registers .............................................................36 Figure 2.7-1 Configuration of dedicated registers ......................................................................................39 Figure 2.7-2 Data transfer to the accumulator ...........................................................................................40 Figure 2.7-3 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension) 41 Figure 2.7-4 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension) .41 Figure 2.7-5 Example of 32-bit data transfer to the accumulator (A) (register indirect) .............................41 Figure 2.7-6 Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect) .......................42 Figure 2.7-7 Stack operation instruction and stack pointer ........................................................................45 Figure 2.7-8 Processor status (PS) configuration ......................................................................................46 Figure 2.7-9 Condition code register (CCR) configuration .........................................................................48 Figure 2.7-10 Configuration of the register bank pointer (RP) .....................................................................50 Figure 2.7-11 Conversion rules for physical address of general-purpose register area ..............................50 Figure 2.7-12 Configuration of the interrupt level mask register (ILM) ........................................................51 Figure 2.7-13 Program counter (PC) ...........................................................................................................52 Figure 2.7-14 Physical address generation by the direct page register (DPR) ............................................53 Figure 2.7-15 Example of direct page register (DPR) setting and data access ...........................................53 |
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