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TPS61280AYFFR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS61280AYFFR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 54 page  SW PGND SDA PGND SW nBYP AGND PGND TOP VIEW D4 D3 D2 D1 C4 PGND C3 C2 C1 nBYP PGND SW SDA AGND BOTTOM VIEW VSEL SCL VOUT VOUT VOUT B1 B2 B3 B4 VOUT VSEL SCL EN GPIO VIN VIN VIN A1 A2 A3 A4 VIN EN GPIO SW PGND TPS61280A, TPS61281A, TPS61282A SLVSCG9A – MAY 2014 – REVISED SEPTEMBER 2014 www.ti.com 8 Pin Configurations and Functions TPS61280A Pin Functions - TPS61280A PIN I/O DESCRIPTION NAME NO. VIN A3, A4 I Power supply input. VOUT B3, B4 O Boost converter output. This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default values. This input must not be left floating and must be terminated. EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be EN A1 I regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For more details, refer to Table 2. EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more details, refer to Table 2. This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT ) pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be terminated. Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output followed by a start-up phase. GPIO A2 I/O Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edge- triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state. Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced. VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left VSEL B1 I floating and must be terminated. A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to . This pin must nBYP C1 I not be left floating and must be terminated. SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated. SDA C2 I/O Serial interface address/data line. This pin must not be left floating and must be terminated. SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. PGND D2, D3, D4 Power ground pin. AGND D1 Analog ground pin. This is the signal ground reference for the IC. 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TPS61280A TPS61281A TPS61282A |
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