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K9K2G08Q0M-PIB0 Datasheet(PDF) 11 Page - Samsung semiconductor

Part # K9K2G08Q0M-PIB0
Description  256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K9K2G08Q0M-PIB0 Datasheet(HTML) 11 Page - Samsung semiconductor

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FLASH MEMORY
11
K9K2G08Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G16Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-YCB0,YIB0,PCB0,PIB0
K9K2G16U0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-VCB0,VIB0,FCB0,FIB0
CAPACITANCE(TA=25
°C, VCC=1.8V/3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
VALID BLOCK
NOTE :
1. The
K9K2GXXX0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2008
-
2048
Blocks
AC TEST CONDITION
(K9K2GXXX0M-XCB0 :TA=0 to 70
°C, K9K2GXXX0M-XIB0:TA=-40 to 85°C
K9K2GXXQ0M : Vcc=1.70V~1.95V , K9K2GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K2GXXQ0M
K9K2GXXU0M
Input Pulse Levels
0V to Vcc
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
Input and Output Timing Levels
Vcc/2
1.5V
K9K2GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9K2GXXU0M:Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
K9K2GXXU0M:Output Load (Vcc:3.3V +/-10%)
-
1 TTL GATE and CL=100pF
Program / Erase Characteristics
NOTE : 1. Max. time of
tCBSY depends on timing between internal program completion and data in
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
300
700
µs
Dummy Busy Time for Cache Program
tCBSY
3
700
µs
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
4
cycles
Spare Array
-
-
4
cycles
Block Erase Time
tBERS
-
2
3
ms
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
PRE
Mode
H
L
L
H
X
X
Read Mode
Command Input
L
H
L
H
X
X
Address Input(5clock)
H
L
L
H
H
X
Write Mode
Command Input
L
H
L
H
H
X
Address Input(5clock)
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
Data Output
X
X
X
X
H
X
X
During Read(Busy)
X
X
X
X
X
H
X
During Program(Busy)
X
X
X
X
X
H
X
During Erase(Busy)
X
X(1)
X
X
X
L
X
Write Protect
X
X
H
X
X
0V/VCC(2)
0V/VCC(2)
Stand-by


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