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DS90CF561MTD Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DS90CF561MTD Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 12 page DS90CF561 Pin Description — FPD Link Transmitter Pin Name I/O No. Description TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.) TxOUT+ O 3 Positive LVDS differential data output TxOUT− O 3 Negative LVDS differential data output FPSHIFT IN I 1 TTL level clock input. The falling edge acts as data strobe. TxCLK OUT+ O 1 Positive LVDS differential clock output TxCLK OUT− O 1 Negative LVDS differential clock output PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. V CC I 4 Power supply pins for TTL inputs GND I 5 Ground pins for TTL inputs PLL V CC I 1 Power supply pin for PLL PLL GND I 2 Ground pins for PLL LVDS V CC I 1 Power supply pin for LVDS outputs LVDS GND I 3 Ground pins for LVDS outputs DS90CF562 Pin Description — FPD Link Receiver Pin Name I/O No. Description RxIN+ I 3 Positive LVDS differential data inputs RxIN− I 3 Negative LVDS differential data inputs RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE, FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.) RxCLK IN+ I 1 Positive LVDS differential clock input RxCLK IN− I 1 Negative LVDS differential clock input FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe. PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state V CC I 4 Power supply pins for TTL outputs GND I 5 Ground pins for TTL outputs PLL V CC I 1 Power supply for PLL PLL GND I 2 Ground pin for PLL LVDS V CC I 1 Power supply pin for LVDS inputs LVDS GND I 3 Ground pins for LVDS inputs www.national.com 11 |
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